Products incorporating the S5PC will benefit from the rich video and multimedia functions which consumes very low power, enabling longer video playback time with a standard size battery:? High quality real-time video conferencing? The Cortex A8 also provides support for JAVA acceleration, and includes a dedicated vector floating point coprocessor allowing efficient implementation of various encryption schemes and high quality 3D graphics applications. Optimized interface for high memory bandwidth requirements: The S5PC has an optimized interface to external memory capable of sustaining the demanding memory bandwidths required in high-end communication services. Software support to reduce application design time: Existing applications on Samsung application processor families can be ported to the S5PC application processors with minimal changes to the BSP.
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Ryoo J. Land size Via hole Stack-up Reference Patterns Routing Transmission Line Impedance EMI design considerations Recommendations Tips Reflow profile SMT There are two methods for forming the land in PCB. One is the solder mask defined method: The land copperplate is made bigger than its real size, and the solder mask is made in a desired size to determine the land area.
Through this method, it is possible to accurately form the size of land, but relatively routing space is reduced because of large area of copperplate. The other is the non-solder mask defined method: Land size is made smaller than the solder mask to form the land. The Land size is determined according to etching time generated in the course of producing PCB. This method is a little better for routing because of small area of copperplate, compared to the SMD method.
Note: Values on this material are just recommended values and can be changed from PCB manufacture and assembly capability. Using via properly facilitates the layout of parts. In case of highly integrated board, via size becomes more important. It is because the small-sized via allows more routing space and the increased insertion rate of parts.
The through-hole via is the most frequently used type of via. In particular, if the through-hole via is used for FBGA package, via hole matrix is formed on the opposite side of PCB, causing restriction in the layout of trace and component.
See Figure x-1 If you want to facilitate routing on Board and increase the area of insertion for parts, it is more useful to use the following two via techniques. However, it is possible to connect one side of PCB only to the neighboring layer.
In addition, it facilitates both-side insertion because via does not appear on the opposite side of PCB. It is also used to interconnect Micro blind vias. The following examples illustrate the proper use of layers. It is required to extract many signal traces from narrow space and it is not easy for each trace to maintain desired characteristic impedance.
The following figure illustrates the width and interval of trace the user can observe when using the land pad as explained in the previous chapter. In normal case, we recommend the trace width of 0.
If possible, it is recommended to use the broad power plane. But in case of using power patterns, apply line width over 1mm as possible as you can. It gives aid to us not only signal quality but also for avoiding thermal issue too. Strip line The signal line is inserted between upper and lower layer power planes in order to implement transmission line. It is advantageous in that clean signals can be transmitted because the power plane has shield effects on both sides, but it must pass the via in order to connect to the element.
Microstrip line The signal line is placed on the outer layer and ground plane is placed at the next neighboring layer. This is easier to implement than the Strip line. The following example illustrates characteristic impedance of the two transmission lines. If dcap lacks capacity or supplied path impedance is too high, switching noise is generated and it becomes the source of radiation.
Dcap must use a proper capacitor type according to the frequency. If possible, the decoupling capacitor must be basically placed closer to the power pin of a desired device. When using PCB pad, in addition, do not connect more than 2 decoupling capacitors to one via. The following list the general layout guidelines for the critical signals such as clocks and strobes.
Minimize crossovers between voltage islands for high-speed signals. Minimize the use of vias to connect between signal traces. Clock signals should be routed on the layer, which is adjacent to the ground layer. It is recommended that the space from one clock trace to other traces is at least 20 mils Mutualclearness and the space from one segment of each clock net to other segments of the same clock net is at least 50 mils self-clearness. Keep clock traces away from the discontinuity of its reference plane to reduce EMI noise.
Be careful when one clock source drives more than one clock load. The board design guidelines handle trace separation, termination placement requirements and overall trace length guidelines. When an engineer lays out a new design, the excellent signal quality and minimized EMI problem must be required.
That is based on four layer board. The first layer is for signal layer. The second layer is for ground. The third layer is for power and the fourth layer is for signal layer again.
We should basically consider the following instruction. HS signals should be placed on top shown in the below figure. Route high-speed USB signals not using Vias and stubs with using two 45 degree turns or an arc instead of making a single 90 degree turn. This reduces signal reflections and impedance changes that affect signal quality. Avoid crossing over antietch if at all possible.
Their parallelism between USB differential signals with the trace spacing should be maintained. The deviation should be minimized. The minimized length of high speed clock and periodic signal traces is highly recommended. So, all capacitance including the board parasitic must be smaller than 15pF. Minimize the branch length. Maximum the length: under 45mm. Route most segments in inner layer. Power signal must be reinforced as soon as possible. Also, the bypass capacitors have to be located closely to the power pads.
Place 2 more decoupling capacitors for power net per a DRAM. Recommended differential impedance is ohm. T-branch topology is recommenced for Command, Address and Control net. Pattern Length guidelines According to line impedance and drive strength, pattern length is put in the range of value described as below. The impedance matching problem must be taken care. The characteristic impedance of the differential signal pair should be 50?
Generally, to achieve the characteristic impedance mentioned above, the line width of each of the differential signal pair is about 8 mils and the space between them is 10mil when the height between the copper layer and the GND plane is 6mil in 4 layer PCB board. Special bypassing is recommended for the high speed power supply pins due to their sensitivity to power supply noise coupling.
These power pins supply internal analog and clock generation blocks and are sensitive to power supply noise. Attention should be paid to proper isolation and bypassing of these pins.
All bypass capacitors should be connected to the power and ground plane with a low inductance connection The bulk bypass capacitor s should have good high frequency characteristics. It should be located close to the source of the power output pin of regulator or connector pin for off board regulators.
Local high frequency bypass should also be implemented. The following capacitor is recommended for local bypass: Ceramic X7R Dielectric - 0. The paired capacitors must be located as close as possible to each other. The following values are recommended for the capacitor pairs: Ceramic X7R Dielectric - 0.
If this resistance is large, there would be an IR drop in the board. This chapter provides some tips to reduce EMI. Recommendations Tips The following general guidelines Including the guidelines mentioned above chapters in this Layout guide document should be applied to system implementation: Component placement can influence on the amount of EMI levels.
Place all components associated with one clock trace closely together. This reduces the trace length and reduces radiation. Place high-current devices as closely as possible to the power sources. High current device should be located as closely to the source circuitry.
[Q] SEC S5PC110 Test B/D